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100 mA, Low Quiescent Current, CMOS Linear Regulator ADP120
FEATURES
Input voltage range: 2.3 V to 5.5 V Output voltage range: 1.2 V to 3.3 V Output current: 100 mA Low quiescent current IGND = 11 A with zero load IGND = 22 A with 100 mA load Low shutdown current: <1 A Low dropout voltage 60 mV @ 100 mA load High PSRR 73 dB @ 1 kHz at VOUT = 1.2 V 70 dB @ 10 kHz at VOUT = 1.2 V Low noise: 40 V rms at VOUT = 1.2 V No noise bypass capacitor required Initial accuracy: 1% Stable with small 1 F ceramic output capacitor 16 fixed output voltage options Current-limit and thermal overload protection Logic controlled enable 5-lead TSOT package 4-ball 0.4 mm pitch WLCSP
TYPICAL APPLICATIONS CIRCUITS
VIN = 2.3V
1
VIN GND EN
VOUT 5
VOUT = 1.8V + 1F
+ 1F
2 3
NC = NO CONNECT
Figure 1. ADP120 TSOT with Fixed Output Voltage, 1.8 V
VIN = 2.3V + 1F VIN VOUT
VOUT = 1.8V + 1F
07589-001
NC 4
EN
GND
Figure 2. ADP120 WLCSP with Fixed Output Voltage, 1.8 V
APPLICATIONS
Mobile phones Digital camera and audio devices Portable and battery-powered equipment Post regulation
GENERAL DESCRIPTION
The ADP120 is a low quiescent current, low dropout, linear regulator that operates from 2.3 V to 5.5 V and provides up to 100 mA of output current. The low 60 mV dropout voltage at 100 mA load improves efficiency and allows operation over a wide input voltage range. The low 25 A of quiescent current at full load makes the ADP120 ideal for battery-operated portable equipment. The ADP120 is available in 16 fixed output voltage options, ranging from 1.2 V to 3.3 V. The part is optimized for stable operation with small 1 F ceramic output capacitors. The ADP120 delivers good transient performance with minimal board area. Short-circuit protection and thermal overload protection circuits prevent damage in adverse conditions. The ADP120 is available in a tiny 5-lead TSOT and a 4-ball 0.4 mm pitch WLCSP for the smallest footprint solution for use in a variety of portable applications.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07589-002
ADP120 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Application Circuits............................................................ 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Recommended Specifications: Input and Output Capacitors 4 Absolute Maximum Ratings............................................................ 5 Thermal Data ................................................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ..............................................7 Theory of Operation ...................................................................... 11 Applications Information .............................................................. 12 Capacitor Selection .................................................................... 12 Undervoltage Lockout ............................................................... 13 Enable Feature ............................................................................ 13 Current Limit and Thermal Overload Protection ................. 14 Thermal Considerations............................................................ 14 PCB Layout Considerations ...................................................... 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 19
REVISION HISTORY
7/08--Rev. 0 to Rev. A Deleted ADP120-1.............................................................. Universal Changes to General Description .................................................... 1 Changes to Dropout Voltage Parameter, Table 1 .......................... 3 Changes to Thermal Data Section.................................................. 5 Changes to Figure 12 and Figure 14 ............................................... 8 Changes to Figure 22 ........................................................................ 9 Changes to Table 6 and Table 7 ..................................................... 14 Changes to Figure 46 and Figure 47 Captions ............................ 17 Changes to Ordering Guide .......................................................... 18 6/08--Revision 0: Initial Version
Rev. A | Page 2 of 20
ADP120 SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 2.3 V, whichever is greater; EN = VIN, IOUT = 10 mA, CIN = COUT = 1 F, TA = 25C, unless otherwise noted. Table 1.
Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Symbol VIN IGND Conditions TJ = -40C to +125C IOUT = 0 A IOUT = 0 A, TJ = -40C to +125C IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 100 mA IOUT = 100 mA, TJ = -40C to +125C EN = GND EN = GND, TJ = -40C to +125C IOUT = 10 mA 100 A < IOUT < 100 mA, VIN = (VOUT + 0.4 V) to 5.5 V 100 A < IOUT < 100 mA, VIN = (VOUT + 0.4 V) to 5.5 V, TJ = -40C to +125C VIN = (VOUT + 0.4 V) to 5.5 V, IOUT = 1 mA, TJ = -40C to +125C IOUT = 1 mA to 100 mA IOUT = 1 mA to 100 mA, TJ = -40C to +125C VOUT = 3.3 V IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 100 mA IOUT = 100 mA, TJ = -40C to +125C IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 100 mA IOUT = 100 mA, TJ = -40C to +125C VOUT = 3.3 V Min 2.3 Typ 11 21 15 29 22 35 0.1 -1 -2 -2.5 1.5 +1 +2 +2.5 Max 5.5 Unit V A A A A A A A A % % %
SHUTDOWN CURRENT FIXED OUTPUT VOLTAGE ACCURACY
IGND-SD VOUT
REGULATION Line Regulation Load Regulation 1 DROPOUT VOLTAGE 2 TSOT
VOUT/VIN VOUT/IOUT VDROPOUT
-0.03 0.001
+0.03
%/ V %/mA %/mA mV mV mV mV mV mV mV mV s mA C C V V A A V V mV V rms V rms V rms
0.005 8 12 80 120 6 9 60 90 110 120 180 150 15 1.2 0.4 0.05 1 2.25 1.5 120 65 52 40 350
WLCSP
START-UP TIME 3 CURRENT LIMIT THRESHOLD 4 THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis EN INPUT EN Input Logic High EN Input Logic Low EN Input Leakage Current UNDERVOLTAGE LOCKOUT Input Voltage Rising Input Voltage Falling Hysteresis OUTPUT NOISE
tSTART-UP ILIMIT TSSD TSSD-HYS VIH VIL VI-LEAKAGE UVLO UVLORISE UVLOFALL UVLOHYS OUTNOISE
TJ rising
2.3 V VIN 5.5 V 2.3 V VIN 5.5 V EN = VIN or GND EN = VIN or GND, TJ = -40C to +125C TJ = -40C to +125C TJ = -40C to +125C 10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V 10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.5 V 10 Hz to 100 kHz, VIN = 5 V, VOUT = 1.2 V
Rev. A | Page 3 of 20
ADP120
Parameter POWER SUPPLY REJECTION RATIO Symbol PSRR Conditions 10 kHz, VIN = 5 V, VOUT = 3.3 V 10 kHz, VIN = 5 V, VOUT = 2.5 V 10 kHz, VIN = 5 V, VOUT = 1.2 V Min Typ 60 66 70 Max Unit dB dB dB
1 2
Based on an endpoint calculation using 1 mA and 100 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.3 V. 3 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value. 4 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITORS
Table 2.
Parameter MINIMUM INPUT AND OUTPUT CAPACITANCE 1 CAPACITOR ESR
1
Symbol CMIN RESR
Conditions TJ = -40C to +125C TJ = -40C to +125C
Min 0.70 0.001
Typ
Max 1
Unit F
The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended, Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. A | Page 4 of 20
ADP120 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VIN to GND Pins VOUT to GND Pins EN to GND Pins Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating -0.3 V to +6 V -0.3 V to VIN -0.3 V to +6 V -65C to +150C -40C to +125C JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a four-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of JA are based on a four-layer, 4 in. x 3 in. PCB. Refer to JESD 51-7 and JESD 51-9 for detailed information regarding board construction. For additional information, see Application Note AN-617, MicroCSPTM Wafer Level Chip Scale Package. JB is the junction-to-board thermal characterization parameter with units of C/W. JB of the package is based on modeling and calculation using a four-layer board. JESD51-12, Guidelines for Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, JB. Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package, factors that make JB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD x JB) Refer to JESD51-8, JESD51-9, and JESD51-12 for more detailed information about JB.
THERMAL DATA
Absolute maximum ratings apply individually only, not in combination. The ADP120 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (JA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula TJ = TA + (PD x JA)
THERMAL RESISTANCE
JA and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance
Package Type 5-Lead TSOT 4-Ball, 0.4 mm Pitch WLCSP JA 170 260 JB 43 58 Unit C/W C/W
ESD CAUTION
Rev. A | Page 5 of 20
ADP120 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1 2 VOUT
VIN 1 GND 2 EN 3 TOP VIEW (Not to Scale)
5
VOUT
A VIN
07589-033
4
NC
TOP VIEW (Not to Scale) B EN GND
07589-034
NC = NO CONNECT
Figure 3. 5-Lead TSOT Pin Configuration
Figure 4. 4-Ball WLCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. TSOT WLCSP 1 A1 2 B2 3 B1 4 5 N/A A2 Mnemonic VIN GND EN NC VOUT Description Regulator Input Supply. Bypass VIN to GND with a 1 F or greater capacitor. Ground. Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. No Connect. Not connected internally. Not applicable (N/A) for the WLCSP. Regulated Output Voltage. Bypass VOUT to GND with a 1 F or greater capacitor.
Rev. A | Page 6 of 20
ADP120 TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 1 F, TA = 25C, unless otherwise noted.
1.804 1.802 1.800
VOUT (V)
GROUND CURRENT (A)
LOAD = 10A LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA
35 30 25 20 15 10 5 0 -40C -5C 25C TJ (C) 85C 125C
07589-008
1.798 1.796 1.794 1.792 1.790 -40C -5C 25C TJ (C) 85C 125C
07589-005
LOAD = 10A LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA
Figure 5. Output Voltage vs. Junction Temperature
1.805
Figure 8. Ground Current vs. Junction Temperature
30
1.803
25
GROUND CURRENT (A)
20
VOUT (V)
1.801
15
1.799
10
1.797
5
07589-006
0.1
1 ILOAD (mA)
10
100
0.1
1 ILOAD (mA)
10
100
Figure 6. Output Voltage vs. Load Current
1.805 LOAD = 10A LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA
Figure 9. Ground Current vs. Load Current
30
1.803
25
GROUND CURRENT (A)
20
VOUT (V)
1.801
15
1.799
10 LOAD = 10A LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA
07589-010
1.797
5
VIN (V)
07589-007
1.795 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
0 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 VIN (V)
Figure 7. Output Voltage vs. Input Voltage
Figure 10. Ground Current vs. Input Voltage
Rev. A | Page 7 of 20
07589-009
1.795 0.01
0 0.01
ADP120
0.35 0.30
SHUTDOWN CURRENT (A)
90
2.30V 2.50V 3.00V 3.50V 4.20V 5.50V
TA = 25C
80
DROPOUT VOLTAGE (mV)
70 60 50 40 VOUT = 2.5V 30 20 10 VOUT = 3.3V
0.25 0.20 0.15 0.10 0.05 0 -50
07589-011
0 1 10 ILOAD (mA) 100
07589-014 07589-016 07589-015
-25
0
25
50
75
100
125
TEMPERATURE (C)
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
120
Figure 14. Dropout Voltage vs. Load Current, WLCSP, VOUT = 2.5 V and 3.3 V
3.35
TA = 25C
100
DROPOUT VOLTAGE (mV)
3.30
80
VOUT (V)
3.25
60
3.20
40 VOUT = 2.5V 20 VOUT = 3.3V 0
07589-012
3.15 VOUT @ 1mA VOUT @ 10mA VOUT @ 20mA VOUT @ 50mA VOUT @ 100mA 3.25 3.30 3.35 3.40 VIN (V) 3.45 3.50 3.55 3.60
3.10
1
10 ILOAD (mA)
100
3.05 3.20
Figure 12. Dropout Voltage vs. Load Current, TSOT, VOUT = 2.5 V and 3.3 V
3.35
Figure 15. Output Voltage vs. Input Voltage (in Dropout), WLCSP, VOUT = 3.3 V
60
3.30
GROUND CURRENT (A)
50
ILOAD @ 1mA ILOAD @ 10mA ILOAD @ 20mA ILOAD @ 50mA ILOAD @ 100mA
3.25
VOUT (V)
40
3.20
30
3.15 VOUT VOUT VOUT VOUT VOUT 3.25 3.30 3.35 3.40 VIN (V) 3.45 3.50 @ 1mA @ 10mA @ 20mA @ 50mA @ 100mA 3.55 3.60
07589-013
20
3.10
10
3.05 3.20
0 3.20
3.25
3.30
3.35
3.40 VIN (V)
3.45
3.50
3.55
3.60
Figure 13. Output Voltage vs. Input Voltage (in Dropout), TSOT, VOUT = 3.3 V
Figure 16. Ground Current vs. Input Voltage (in Dropout)
Rev. A | Page 8 of 20
ADP120
0 -10 -20 -30
PSRR (dB) PSRR (dB)
100mA 10mA 1mA 100A NO LOAD
VRIPPLE = 50mV VIN = 5V VOUT = 1.2V COUT = 1F
0 3.3V/100mA -10 -20 -30 -40 -50 -60 -70 -80 -90
07589-017 07589-020 07589-022 07589-021
1.2V/100mA 1.2V/100A
1.8V/100mA 1.8V/100A
3.3V/100A
-40 -50 -60 -70 -80 -90 -100 10
100
1k
10k
100k
1M
10M
-100 10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Power Supply Rejection Ratio vs. Frequency
0 -10 -20 -30
PSRR (dB)
Figure 20. Power Supply Rejection Ratio vs. Frequency, Various Output Voltages and Load Currents
10
100mA 10mA 1mA 100A NO LOAD
VRIPPLE = 50mV VIN = 5V VOUT = 1.8V COUT = 1F
3.3V
NOISE (V/ Hz)
1
1.8V
-40 -50 -60 -70 -80 -90
07589-018
1.2V
0.1
-100 10
100
1k
10k
100k
1M
10M
0.01 10
100
1k FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 18. Power Supply Rejection Ratio vs. Frequency
Figure 21. Output Noise Spectrum, VIN = 5 V, ILOAD = 10 mA, COUT = 1 F
0 -10 -20 -30
PSRR (dB)
100mA 10mA 1mA 100A NO LOAD
VRIPPLE = 50mV VIN = 5V VOUT = 3.3V COUT = 1F
70 3.3V 60 2.5V 50
NOISE (V rms)
1.8V 1.5V 1.2V
-40 -50 -60 -70 -80
40 30 20 10
-90
07589-019
-100 10
100
1k
10k
100k
1M
10M
0 0.001
0.01
0.1 ILOAD (mA)
1
10
100
FREQUENCY (Hz)
Figure 19. Power Supply Rejection Ratio vs. Frequency
Figure 22. Output Noise vs. Load Current and Output Voltage VIN = 5 V, COUT = 1 F
Rev. A | Page 9 of 20
ADP120
ILOAD
(100mA/DIV)
ILOAD
(1V/DIV)
1mA TO 100mA LOAD STEP, 2.5A/s
4V TO 5V INPUT VOLTAGE STEP, 2V/s
VOUT
(50mV/DIV) (10mV/DIV)
VOUT
07589-023
(40s/DIV)
(4s/DIV)
Figure 23. Load Transient Response, CIN and COUT = 1 F
Figure 25. Line Transient Response, Load Current = 100 mA
ILOAD
(100mA/DIV)
1mA TO 100mA LOAD STEP, 2.5A/s
(1V/DIV)
ILOAD 4V TO 5V INPUT VOLTAGE STEP, 2V/s
VOUT
(50mV/DIV) (10mV/DIV)
VOUT
07589-024
(40s/DIV)
(10s/DIV)
Figure 24. Load Transient Response, CIN and COUT = 4.7 F
Figure 26. Line Transient Response, Load Current = 1 mA
Rev. A | Page 10 of 20
07589-026
VIN = 5V VOUT = 1.8V
VOUT = 1.8V, CIN = COUT = 1F
07589-125
VIN = 5V VOUT = 1.8V
VOUT = 1.8V, CIN = COUT = 1F
ADP120 THEORY OF OPERATION
The ADP120 is a low quiescent current, low dropout linear regulator that operates from 2.3 V to 5.5 V and provides up to 100 mA of output current. Drawing a low 22 A of quiescent current (typical) at full load makes the ADP120 ideal for battery-operated portable equipment. Shutdown current consumption is typically 100 nA. Optimized for use with small 1 F ceramic capacitors, the ADP120 provides excellent transient performance.
VIN R1 GND SHORT CIRCUIT, UVLO, AND THERMAL PROTECT VOUT
Internally, the ADP120 consists of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. The ADP120 is available in 16 output voltage options, ranging from 1.2 V to 3.3 V. The ADP120 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on; when EN is low, VOUT turns off. For automatic startup, EN can be tied to VIN.
EN
SHUTDOWN
0.8V REFERENCE
Figure 27. Internal Block Diagram
07589-127
R2
Rev. A | Page 11 of 20
ADP120 APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP120 is designed for operation with small, space-saving ceramic capacitors, but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 F capacitance with an ESR of 1 or less is recommended to ensure stability of the ADP120. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP120 to large changes in load current. Figure 28 and Figure 29 show the transient responses for output capacitance values of 1 F and 4.7 F, respectively.
ILOAD
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP120, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 30 depicts the capacitance vs. voltage bias characteristic of a 0402 1 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about 15% over the -40C to +85C temperature range and is not a function of package or voltage rating.
1.2 MURATA PART NUMBER: GRM155R61A105KE15
(100mA/DIV)
1mA TO 100mA LOAD STEP, 2.5A/s
(50mV/DIV)
1.0
CAPACITANCE (F)
VOUT VOUT = 1.8V, CIN = COUT = 1F (400ns/DIV)
0.8
07589-128
0.6
Figure 28. Output Transient Response, COUT = 1 F
ILOAD
0.4
0.2
(100mA/DIV)
2
4 6 VOLTAGE (V)
8
10
Figure 30. Capacitance vs. Voltage Characteristic
(50mV/DIV)
VOUT
Use Equation 1 to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) (1) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.94 F at 1.8 V, as shown in Figure 30. Substituting these values in Equation 1 yields CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F
07589-129
VOUT = 1.8V, CIN = COUT = 4.7F (400ns/DIV)
Figure 29. Output Transient Response, COUT = 4.7 F
Input Bypass Capacitor
Connecting a 1 F capacitor from VIN to GND reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance are encountered. If greater than 1 F of output capacitance is required, increase the input capacitor to match it.
Rev. A | Page 12 of 20
07589-126
1mA TO 100mA LOAD STEP, 2.5A/s
0 0
ADP120
Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP120, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.
1.10 1.05
TYPICAL EN THRESHOLDS (V)
1.00 0.95 EN ACTIVE 0.90 0.85 EN INACTIVE 0.80 0.75 0.70 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 VIN (V)
UNDERVOLTAGE LOCKOUT
The ADP120 has an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately 2.2 V. This ensures that the inputs and the output of the ADP120 behave in a predictable manner during power-up.
ENABLE FEATURE
The ADP120 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 31, when a rising voltage on EN crosses the active threshold, VOUT turns on. When a falling voltage on EN crosses the inactive threshold, VOUT turns off.
Figure 32. Typical EN Pin Thresholds vs. Input Voltage
The ADP120 utilizes an internal soft start to limit the inrush current when the output is enabled. The start-up time for the 1.8 V option is approximately 120 s from the time the EN active threshold is crossed to when the output reaches 90% of its final value. The start-up time is somewhat dependent on the output voltage setting and increases slightly as the output voltage increases.
6 EN
VOUT
(500mV/DIV)
5
EN
4
CURRENT (V)
3.3V 3
07589-124
VIN = 5V VOUT = 1.8V CIN = COUT = 1F ILOAD = 100mA (40ms/DIV)
2
1.8V 1.2V
1
Figure 31. Typical EN Pin Operation
As shown in Figure 31, the EN pin has hysteresis built-in. This prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. The EN pin active/inactive thresholds are derived from the VIN voltage; therefore, these thresholds vary with changing input voltage. Figure 32 shows typical EN active/inactive thresholds when the input voltage varies from 2.3 V to 5.5 V.
0
20
40
60
80
100
120
140
160
180
200
TIME (s)
Figure 33. Typical Start-Up Time
Rev. A | Page 13 of 20
07589-133
0
07589-025
ADP120
CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION
The ADP120 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP120 is designed to current limit when the output load reaches 150 mA (typical). When the output load exceeds 150 mA, the output voltage reduces to maintain a constant current limit. Thermal overload protection is built-in, limiting the junction temperature to a maximum of 150C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150C, the output turns off, reducing the output current to zero. When the junction temperature drops below 135C, the output turns on again thereby restoring output current to its nominal value. Consider the case where a hard short from VOUT to GND occurs. At first, the ADP120 current limits, conducting only 150 mA into the short. If self-heating of the junction is great enough to cause its temperature to rise above 150C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 135C, the output turns on and conducts 150 mA into the short, again causing the junction temperature to rise above 150C. This thermal oscillation between 135C and 150C causes a current oscillation between 150 mA and 0 mA that continues as long as the short remains at the output. Current- and thermal-limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited to prevent junction temperatures from exceeding 125C. temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (JA). The JA number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pins to the PCB. Table 6 shows typical JA values of the 5-lead TSOT and 4-ball WLCSP packages for various PCB copper sizes. Table 7 shows the typical JB value of the 5-lead TSOT and 4-ball WLCSP. Table 6. Typical JA Values
Copper Size (mm ) 01 50 100 300 500
1
2
TSOT 170 152 146 134 131
JA (C/W) WLCSP 260 159 157 153 151
Device soldered to minimum size pin traces.
Table 7. Typical JB Values
TSOT 42.8 JB (C/W) WLCSP 58.4
The junction temperature of the ADP120 can be calculated from the following equation: TJ = TA + (PD x JA) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN - VOUT) x ILOAD] + (VIN x IGND) where: ILOAD is the load current. IGND is the ground current. VIN and VOUT are input and output voltages, respectively. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to the following: TJ = TA + {[(VIN - VOUT) x ILOAD] x JA} (4) As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure the junction temperature does not rise above 125C. The following figures show junction temperature calculations for different ambient temperatures, load currents, VIN-to-VOUT differentials, and areas of PCB copper. (3) (2)
THERMAL CONSIDERATIONS
In most applications, the ADP120 does not dissipate much heat due to its high efficiency. However, in applications with high ambient temperature and high supply voltage-to-output voltage differential, the heat dissipated in the package is large enough to cause the junction temperature of the die to exceed the maximum junction temperature of 125C. When the junction temperature exceeds 150C, the converter enters thermal shutdown. It recovers only after the junction temperature has decreased below 135C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2. To guarantee reliable operation, the junction temperature of the ADP120 must not exceed 125C. To ensure the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction
Rev. A | Page 14 of 20
ADP120
140 MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (C) JUNCTION TEMPERATURE, TJ (C)
140 MAX JUNCTION TEMPERATURE 120 IL = 100mA 100 80 60 40 20 0 0.5 IL = 10mA IL = 75mA IL = 50mA IL = 25mA
120 100 80 60 40 20 0 0.5 IL = 100mA IL = 75mA IL = 50mA IL = 25mA
IL = 1mA
IL = 10mA
IL = 1mA
07589-134
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN - VOUT (V)
VIN - VOUT (V)
Figure 34. TSOT, 500 mm2 of PCB Copper, TA = 25C
140 MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (C) JUNCTION TEMPERATURE, TJ (C)
Figure 37. TSOT, 500 mm2 of PCB Copper, TA = 50C
140 MAX JUNCTION TEMPERATURE 120 IL = 100mA 100 80 60 40 20 0 0.5 IL = 75mA IL = 50mA IL = 25mA
120 100 IL = 100mA 80 60 40 20 0 0.5 IL = 75mA IL = 50mA IL = 25mA
IL = 10mA
IL = 1mA
IL = 10mA
IL = 1mA
07589-027
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN - VOUT (V)
VIN - VOUT (V)
Figure 35. TSOT, 100 mm2 of PCB Copper, TA = 25C
140 MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (C) JUNCTION TEMPERATURE, TJ (C)
Figure 38. TSOT, 100 mm2 of PCB Copper, TA = 50C
140 MAX JUNCTION TEMPERATURE 120 IL = 100mA 100 IL = 50mA 80 IL = 25mA 60 40 20 0 0.5 IL = 10mA IL = 1mA IL = 75mA
120 100 80 60 40 20 0 0.5 IL = 100mA IL = 75mA IL = 50mA IL = 25mA
IL = 10mA 1.0 1.5 2.0 2.5 3.0 3.5
IL = 1mA
07589-028
4.0
4.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN - VOUT (V)
VIN - VOUT (V)
Figure 36. TSOT, 0 mm2 of PCB Copper, TA = 25C
Figure 39. TSOT, 0 mm2 of PCB Copper, TA = 50C
Rev. A | Page 15 of 20
07589-031
07589-030
07589-137
ADP120
140 MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (C)
JUNCTION TEMPERATURE, TJ (C)
140 MAX JUNCTION TEMPERATURE 120 IL = 100mA 100 80 60 40 20 0 0.5 IL = 75mA IL = 50mA IL = 25mA
120 100 IL = 100mA 80 60 40 20 0 0.5 IL = 75mA IL = 50mA IL = 25mA
IL = 10mA
IL = 1mA
IL = 10mA
IL = 1mA
07589-140
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN - VOUT (V)
VIN - VOUT (V)
Figure 40. WLCSP, 500 mm2 of PCB Copper, TA = 25C
140 MAX JUNCTION TEMPERATURE
JUNCTION TEMPERATURE, TJ (C)
JUNCTION TEMPERATURE, TJ (C)
140
Figure 43. WLCSP, 500 mm2 of PCB Copper, TA = 50C
MAX JUNCTION TEMPERATURE 120 IL = 100mA 100 80 IL = 25mA 60 40 20 0 0.5 IL = 75mA IL = 50mA
120 100 80 60 40 20 IL = 10mA 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 IL = 1mA
07589-141
IL = 100mA IL = 75mA IL = 50mA IL = 25mA
IL = 10mA
IL = 1mA
4.0
4.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN - VOUT (V)
VIN - VOUT (V)
Figure 41. WLCSP, 100 mm2 of PCB Copper, TA = 25C
140 MAX JUNCTION TEMPERATURE 120 IL = 100mA 100 80 60 40 20 IL = 10mA 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 IL = 1mA
07589-142
Figure 44. WLCSP, 100 mm2 of PCB Copper, TA = 50C
140 MAX JUNCTION TEMPERATURE 120 100 IL = 50mA 80 IL = 25mA 60 40 20 0 0.5 IL = 10mA
JUNCTION TEMPERATURE, TJ (C)
IL = 75mA
JUNCTION TEMPERATURE, TJ (C)
IL = 100mA
IL = 75mA
IL = 50mA
IL = 25mA
IL = 1mA
4.0
4.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN - VOUT (V)
VIN - VOUT (V)
Figure 42. WLCSP, 0 mm2 of PCB Copper, TA = 25C
Figure 45. WLCSP, 0 mm2 of PCB Copper, TA = 50C
Rev. A | Page 16 of 20
07589-145
07589-144
07589-143
ADP120
In cases where the board temperature is known, use the thermal characterization parameter, JB, to estimate the junction temperature rise. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD x JB)
140 MAX JUNCTION TEMPERATURE 120 IL = 100mA 100 80 IL = 25mA 60 40 20 0 0.5 IL = 10mA IL = 1mA IL = 75mA IL = 50mA
PCB LAYOUT CONSIDERATIONS
Improve heat dissipation from the package by increasing the amount of copper attached to the pins of the ADP120. However, as listed in Table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitor as close as possible to the VOUT and GND pins. Use of 0402- or 0603-size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited.
GND ANALOG DEVICES ADP120-xx-EVALZ GND
(5)
JUNCTION TEMPERATURE, TJ (C)
C1
U1
C2
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN - VOUT (V)
Figure 46. TSOT, TB = 85C
140 MAX JUNCTION TEMPERATURE 120 IL = 100mA 100 80 IL = 25mA 60 40 20 0 0.5 IL = 10mA IL = 1mA IL = 75mA IL = 50mA
07589-146
J1 VIN VOUT
JUNCTION TEMPERATURE, TJ (C)
GND
EN
GND
Figure 48. TSOT PCB Layout
ADP120CB-xx-EVALZ
VIN C1
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
07589-147
J1 VOUT U1
WLC SP
C2
VIN - VOUT (V)
Figure 47. WLCSP, TB = 85C
GND EN
GND
07589-032
Figure 49. WLCSP PCB Layout
Rev. A | Page 17 of 20
07589-136
ADP120 OUTLINE DIMENSIONS
2.90 BSC
5
4
1.60 BSC
1 2 3
2.80 BSC
PIN 1 0.95 BSC *0.90 0.87 0.84 1.90 BSC
*1.00 MAX
0.20 0.08 8 4 0 0.60 0.45 0.30
0.10 MAX
0.50 0.30
SEATING PLANE
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 50. 5-Lead Thin Small Outline Transistor Package [TSOT] (UJ-5) Dimensions shown in millimeters
A1 BALL CORNER
0.860 0.820 SQ 0.780
0.660 0.600 0.540 SEATING PLANE 0.280 0.260 0.240 0.40 BALL PITCH
2 1 A
B
TOP VIEW
(BALL SIDE DOWN)
Figure 51. 4-Ball Wafer Level Chip Scale Package [WLCSP] (CB-4-2) Dimensions shown in millimeters
Rev. A | Page 18 of 20
101507-A
0.230 0.200 0.170
BOTTOM VIEW
(BALL SIDE UP)
0.050 NOM COPLANARITY
ADP120
ORDERING GUIDE
Model ADP120-AUJZ12R7 2 ADP120-AUJZ15R72 ADP120-AUJZ18R72 ADP120-AUJZ33R72 ADP120-ACBZ12R72 ADP120-ACBZ15R72 ADP120-ACBZ155R72 ADP120-ACBZ16R72 ADP120-ACBZ165R72 ADP120-ACBZ17R72 ADP120-ACBZ175R72 ADP120-ACBZ18R72 ADP120-ACBZ188R72 ADP120-ACBZ20R72 ADP120-ACBZ25R72 ADP120-ACBZ278R72 ADP120-ACBZ28R72 ADP120-ACBZ29R72 ADP120-ACBZ30R72 ADP120-ACBZ33R72 ADP120-33-EVALZ2 ADP120-18-EVALZ2 ADP120-15-EVALZ2 ADP120-12-EVALZ2 ADP120CB-2.8-EVALZ2 ADP120CB-2.5-EVALZ2 ADP120CB-1.8-EVALZ2 ADP120CB-1.5-EVALZ2 ADP120CB-1.2-EVALZ2
1 2
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Output Voltage (V) 1 1.2 1.5 1.8 3.3 1.2 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.875 2.0 2.5 2.775 2.8 2.9 3.0 3.3 3.3 1.8 1.5 1.2 2.8 2.5 1.8 1.5 1.2
Package Description 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP 4-Ball WLCSP ADP120 3.3 V Output Evaluation Board ADP120 1.8 V Output Evaluation Board ADP120 1.5 V Output Evaluation Board ADP120 1.2 V Output Evaluation Board ADP120 WLCSP 2.8 V Output Evaluation Board ADP120 WLCSP 2.5 V Output Evaluation Board ADP120 WLCSP 1.8 V Output Evaluation Board ADP120 WLCSP 1.5 V Output Evaluation Board ADP120 WLCSP 1.2 V Output Evaluation Board
Package Option UJ-5 UJ-5 UJ-5 UJ-5 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2 CB-4-2
Branding L9R L9Q L9P L9N LBJ LBK LBL LBM LBN LBP LBQ LBR LBS LBT LBU LBV LBW LBX LBY LBZ
For additional voltage options, contact your local Analog Devices, Inc., sales or distribution representative.
Z = RoHS Compliant Part.
Rev. A | Page 19 of 20
ADP120 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07589-0-7/08(0)
Rev. A | Page 20 of 20

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